Conventionally, in order to amplify analog voltage precisely, an amplifier circuit using an operational amplifier has been used. However, due to a decrease in power supply voltage accompanying with recent miniaturization of a CMOS process, a problem has emerged that voltage amplitude is reduced and S/N (Signal-to-Noise ratio) is deteriorated.
As a countermeasure, a so-called fully differential amplifier circuit has come in use. In the fully differential amplifier circuit, differentiating a signal improves the S/N by obtaining signal amplitude being up to twice as large as the power supply voltage. Further, output impedance of a sensor device that takes information of nature such as light, acceleration, and sound as an analog signal into the circuit is generally high (more than several MΩ). Thus, in order to connect to such a sensor device, it is necessary to connect a non-inverting amplifier circuit that can obtain high input impedance which is more than several GΩ.
FIG. 15 illustrates a conventional circuit of a single end operational amplifier. As the non-inverting amplifier circuit, a configuration of an instrumentation amplifier (an instrumentation amplifier, Non-Patent Literature 1) of FIG. 14 configured using two single end operational amplifiers of FIG. 15 and configurations illustrated in FIGS. 10 and 11 as a symbol of the operational amplifier are exemplified.
Here, an operation of a conventional differential amplifier circuit (e.g., FIG. 14) will be concisely described. Hereinafter, regarding equations (1) to (22), for example, in the case of equations (1) to (4) corresponding to FIG. 14, although electric potentials of an inverting input terminal and an inverting input terminal are expressed as the same description as VINP, it is clear that these are different and the distinction will not be particularly explained. Hereinafter, a differential input voltage is expressed as:VIN=VINP−VINM  (1)
A differential output voltage with respect to VIN is expressed as:VOUT=G·VIN=VOUTP−VOUTM  (2)
Where G is a voltage gain of the amplifier circuit. Note that, for simplicity, the gain of the operation amplifier is assumed to be infinity.
Firstly, the instrumentation amplifier will be described. The instrumentation amplifier includes, as in FIG. 14, two single end operational amplifiers illustrated in FIG. 15 and a resistor network configured with resistors R100, R200, and R201.
IfR200=R201  (3)the gain G is expressed as:G=(R100+2·R200)/R100  (4)Hence, the differential output voltage can be obtained from the equation (2).
Further, a configuration using a double differential operational amplifier shows the same operation.
FIGS. 10 and 11 illustrate a symbol of the double differential operational amplifier.
For FIG. 10,G=1  (5)and for FIG. 11, ifR100=R101  (6)R200=R201  (7)
G is expressed as:G=(R100+R200)/R100  (8)
According to a configuration of the instrumentation amplifier illustrated in FIG. 10, in a non-inverting amplifier circuit, a signal is input to an input terminal of the operational amplifier, and thereby voltage does not remain constant, in contrast to an inverting amplifier circuit in which an input terminal of the operational amplifier is virtually grounded, and thereby voltage remains constant. In particular, when the non-inverting amplifier circuit is connected to a sensor device, a problem arises that its signal amplitude may possibly spread over a wide range. When the signal amplitude spreads over the wide range, as described below, a differential pair may possibly turn off.
To solve the problem, in a circuit of a double differential operational amplifier of FIG. 13, PMOS differential pairs D30 and D40 are respectively connected to two NMOS differential pairs D10 and D20 in parallel. According to this configuration, for the input voltage of the wide range within a range from ground potential to power supply potential, at least either one of NMOS differential pairs or PMOS differential pairs is operated. Therefore, according to this configuration (rail-to-rail), a differential amplification operation is enabled within all of the range from the ground potential to the power supply potential.
Similarly with respect to the single end operational amplifier of FIG. 15, the PMOS differential pair D30 is connected to the NMOS differential pair D10 in parallel. This configuration is also the rail-to-rail configuration, and an amplification operation of a differential signal is enabled within all of the range from the ground potential to the power supply potential.
On the one hand, in a configuration mentioned above in which an NMOS differential pair and a PMOS differential pair are connected in parallel, if mutual conductance of the NMOS differential pair is gmn, and mutual conductance of the PMOS differential pair is gmp, the actual mutual conductance obtained by adding both of the mutual conductances, gmdiff can be expressed as:gmdiff=gmn+gmp  (9)However, for example, when voltage close to the ground potential is input, the NMOS differential pair is turned OFF and becomes unable to operate. Hence, gmn 0, and gmdiff is reduced to as follows:gmdiff≈gmp  (10)
On the other hand, according to similar consideration, when voltage close to the power supply potential is input, the PMOS differential pair is turned OFF and becomes unable to operate. Hence, gmp≈0, and gmdiff goes as follows:gmdiff≈gmn  (11)
In this manner, the mutual conductance of the differential pair of the operational amplifier is widely fluctuated depending on the input voltage. Further, by turning OFF either one of the differential pairs, current flowing through active loads AL101 (FIG. 15) and AL100 (FIG. 13) is changed, and a deterioration in a slew rate and a deterioration in a bandwidth of the operational amplifier are caused.
In Patent Literature 1, in order to restrain an influence on a circuit characteristic given by a fluctuation in an operation state of a differential pair caused by input voltage, a transistor is connected to a single end operational amplifier in parallel to ensure a current path in the case of turning OFF the differential pair. A configuration is proposed in which the transistor prevents current flowing through an active load from fluctuating against the input voltage which turns OFF the differential pair.
Further, in Patent Literature 2, a configuration is proposed in which a fluctuation in mutual conductance of all of differential pairs is restrained. In this configuration, a transistor in which extra current is flown is connected to differential pairs in parallel, and when either one of an NMOS differential pair and a PMOS differential pair is turned OFF, current of the differential pair which is turned ON is increased.